set_property PACKAGE_PIN E8 [get_ports clk_out1_0]
set_property PACKAGE_PIN C5 [get_ports {gpio_in_0[1]}]
set_property PACKAGE_PIN G6 [get_ports {gpio_in_0[0]}]
set_property PACKAGE_PIN C7 [get_ports {gpio_out_0[1]}]
set_property PACKAGE_PIN A6 [get_ports {gpio_out_0[0]}]
set_property PACKAGE_PIN B9 [get_ports {led_0[1]}]
set_property PACKAGE_PIN A9 [get_ports {led_0[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports clk_out1_0]
set_property IOSTANDARD LVCMOS18 [get_ports {gpio_in_0[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {gpio_in_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {gpio_out_0[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {gpio_out_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_0[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_0[0]}]


connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/dvp_0/inst/xsbl2/xsbl_fcnt[0]} {design_1_i/dvp_0/inst/xsbl2/xsbl_fcnt[1]} {design_1_i/dvp_0/inst/xsbl2/xsbl_fcnt[2]} {design_1_i/dvp_0/inst/xsbl2/xsbl_fcnt[3]}]]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/dvp_0/inst/drd_dout[0]} {design_1_i/dvp_0/inst/drd_dout[1]} {design_1_i/dvp_0/inst/drd_dout[2]} {design_1_i/dvp_0/inst/drd_dout[3]} {design_1_i/dvp_0/inst/drd_dout[4]} {design_1_i/dvp_0/inst/drd_dout[5]} {design_1_i/dvp_0/inst/drd_dout[6]} {design_1_i/dvp_0/inst/drd_dout[7]} {design_1_i/dvp_0/inst/drd_dout[8]} {design_1_i/dvp_0/inst/drd_dout[9]} {design_1_i/dvp_0/inst/drd_dout[10]} {design_1_i/dvp_0/inst/drd_dout[11]} {design_1_i/dvp_0/inst/drd_dout[12]} {design_1_i/dvp_0/inst/drd_dout[13]} {design_1_i/dvp_0/inst/drd_dout[14]} {design_1_i/dvp_0/inst/drd_dout[15]} {design_1_i/dvp_0/inst/drd_dout[16]} {design_1_i/dvp_0/inst/drd_dout[17]} {design_1_i/dvp_0/inst/drd_dout[18]} {design_1_i/dvp_0/inst/drd_dout[19]} {design_1_i/dvp_0/inst/drd_dout[20]} {design_1_i/dvp_0/inst/drd_dout[21]} {design_1_i/dvp_0/inst/drd_dout[22]} {design_1_i/dvp_0/inst/drd_dout[23]} {design_1_i/dvp_0/inst/drd_dout[24]} {design_1_i/dvp_0/inst/drd_dout[25]} {design_1_i/dvp_0/inst/drd_dout[26]} {design_1_i/dvp_0/inst/drd_dout[27]} {design_1_i/dvp_0/inst/drd_dout[28]} {design_1_i/dvp_0/inst/drd_dout[29]} {design_1_i/dvp_0/inst/drd_dout[30]} {design_1_i/dvp_0/inst/drd_dout[31]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/dvp_0/inst/dwr_dout[0]} {design_1_i/dvp_0/inst/dwr_dout[1]} {design_1_i/dvp_0/inst/dwr_dout[2]} {design_1_i/dvp_0/inst/dwr_dout[3]} {design_1_i/dvp_0/inst/dwr_dout[4]} {design_1_i/dvp_0/inst/dwr_dout[5]} {design_1_i/dvp_0/inst/dwr_dout[6]} {design_1_i/dvp_0/inst/dwr_dout[7]} {design_1_i/dvp_0/inst/dwr_dout[8]} {design_1_i/dvp_0/inst/dwr_dout[9]} {design_1_i/dvp_0/inst/dwr_dout[10]} {design_1_i/dvp_0/inst/dwr_dout[11]} {design_1_i/dvp_0/inst/dwr_dout[12]} {design_1_i/dvp_0/inst/dwr_dout[13]} {design_1_i/dvp_0/inst/dwr_dout[14]} {design_1_i/dvp_0/inst/dwr_dout[15]} {design_1_i/dvp_0/inst/dwr_dout[16]} {design_1_i/dvp_0/inst/dwr_dout[17]} {design_1_i/dvp_0/inst/dwr_dout[18]} {design_1_i/dvp_0/inst/dwr_dout[19]} {design_1_i/dvp_0/inst/dwr_dout[20]} {design_1_i/dvp_0/inst/dwr_dout[21]} {design_1_i/dvp_0/inst/dwr_dout[22]} {design_1_i/dvp_0/inst/dwr_dout[23]} {design_1_i/dvp_0/inst/dwr_dout[24]} {design_1_i/dvp_0/inst/dwr_dout[25]} {design_1_i/dvp_0/inst/dwr_dout[26]} {design_1_i/dvp_0/inst/dwr_dout[27]} {design_1_i/dvp_0/inst/dwr_dout[28]} {design_1_i/dvp_0/inst/dwr_dout[29]} {design_1_i/dvp_0/inst/dwr_dout[30]} {design_1_i/dvp_0/inst/dwr_dout[31]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/dvp_0/inst/xsblr_dout[0]} {design_1_i/dvp_0/inst/xsblr_dout[1]} {design_1_i/dvp_0/inst/xsblr_dout[2]} {design_1_i/dvp_0/inst/xsblr_dout[3]} {design_1_i/dvp_0/inst/xsblr_dout[4]} {design_1_i/dvp_0/inst/xsblr_dout[5]} {design_1_i/dvp_0/inst/xsblr_dout[6]} {design_1_i/dvp_0/inst/xsblr_dout[7]} {design_1_i/dvp_0/inst/xsblr_dout[8]} {design_1_i/dvp_0/inst/xsblr_dout[9]} {design_1_i/dvp_0/inst/xsblr_dout[10]} {design_1_i/dvp_0/inst/xsblr_dout[11]} {design_1_i/dvp_0/inst/xsblr_dout[12]} {design_1_i/dvp_0/inst/xsblr_dout[13]} {design_1_i/dvp_0/inst/xsblr_dout[14]} {design_1_i/dvp_0/inst/xsblr_dout[15]} {design_1_i/dvp_0/inst/xsblr_dout[16]} {design_1_i/dvp_0/inst/xsblr_dout[17]} {design_1_i/dvp_0/inst/xsblr_dout[18]} {design_1_i/dvp_0/inst/xsblr_dout[19]} {design_1_i/dvp_0/inst/xsblr_dout[20]} {design_1_i/dvp_0/inst/xsblr_dout[21]} {design_1_i/dvp_0/inst/xsblr_dout[22]} {design_1_i/dvp_0/inst/xsblr_dout[23]} {design_1_i/dvp_0/inst/xsblr_dout[24]} {design_1_i/dvp_0/inst/xsblr_dout[25]} {design_1_i/dvp_0/inst/xsblr_dout[26]} {design_1_i/dvp_0/inst/xsblr_dout[27]} {design_1_i/dvp_0/inst/xsblr_dout[28]} {design_1_i/dvp_0/inst/xsblr_dout[29]} {design_1_i/dvp_0/inst/xsblr_dout[30]} {design_1_i/dvp_0/inst/xsblr_dout[31]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/dvp_0/inst/xsblw_dout[0]} {design_1_i/dvp_0/inst/xsblw_dout[1]} {design_1_i/dvp_0/inst/xsblw_dout[2]} {design_1_i/dvp_0/inst/xsblw_dout[3]} {design_1_i/dvp_0/inst/xsblw_dout[4]} {design_1_i/dvp_0/inst/xsblw_dout[5]} {design_1_i/dvp_0/inst/xsblw_dout[6]} {design_1_i/dvp_0/inst/xsblw_dout[7]} {design_1_i/dvp_0/inst/xsblw_dout[8]} {design_1_i/dvp_0/inst/xsblw_dout[9]} {design_1_i/dvp_0/inst/xsblw_dout[10]} {design_1_i/dvp_0/inst/xsblw_dout[11]} {design_1_i/dvp_0/inst/xsblw_dout[12]} {design_1_i/dvp_0/inst/xsblw_dout[13]} {design_1_i/dvp_0/inst/xsblw_dout[14]} {design_1_i/dvp_0/inst/xsblw_dout[15]} {design_1_i/dvp_0/inst/xsblw_dout[16]} {design_1_i/dvp_0/inst/xsblw_dout[17]} {design_1_i/dvp_0/inst/xsblw_dout[18]} {design_1_i/dvp_0/inst/xsblw_dout[19]} {design_1_i/dvp_0/inst/xsblw_dout[20]} {design_1_i/dvp_0/inst/xsblw_dout[21]} {design_1_i/dvp_0/inst/xsblw_dout[22]} {design_1_i/dvp_0/inst/xsblw_dout[23]} {design_1_i/dvp_0/inst/xsblw_dout[24]} {design_1_i/dvp_0/inst/xsblw_dout[25]} {design_1_i/dvp_0/inst/xsblw_dout[26]} {design_1_i/dvp_0/inst/xsblw_dout[27]} {design_1_i/dvp_0/inst/xsblw_dout[28]} {design_1_i/dvp_0/inst/xsblw_dout[29]} {design_1_i/dvp_0/inst/xsblw_dout[30]} {design_1_i/dvp_0/inst/xsblw_dout[31]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/dvp_0/inst/bm/bm_fcnt[0]} {design_1_i/dvp_0/inst/bm/bm_fcnt[1]} {design_1_i/dvp_0/inst/bm/bm_fcnt[2]} {design_1_i/dvp_0/inst/bm/bm_fcnt[3]}]]
connect_debug_port u_ila_0/probe6 [get_nets [list design_1_i/dvp_0/inst/bm/bm_done]]
connect_debug_port u_ila_0/probe7 [get_nets [list design_1_i/dvp_0/inst/bm/bm_on]]
connect_debug_port u_ila_0/probe8 [get_nets [list design_1_i/dvp_0/inst/bm/bm_pend]]
connect_debug_port u_ila_0/probe10 [get_nets [list design_1_i/dvp_0/inst/drd_vout]]
connect_debug_port u_ila_0/probe11 [get_nets [list design_1_i/dvp_0/inst/dwr_vout]]
connect_debug_port u_ila_0/probe13 [get_nets [list design_1_i/dvp_0/inst/xsbl2/sw_start]]
connect_debug_port u_ila_0/probe14 [get_nets [list design_1_i/dvp_0/inst/bm/xsbl_done]]
connect_debug_port u_ila_0/probe15 [get_nets [list design_1_i/dvp_0/inst/xsbl2/xsbl_on]]
connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/dvp_0/inst/xsbl2/xsbl_pend]]
connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/dvp_0/inst/xsbl2/xsbl_start]]
connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/dvp_0/inst/xsblw_vout]]


